- Integer 형을 이용한 10 Counter 를 설계하시오
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mod_10_count IS
PORT(n_cp, n_rd : IN std_logic;
q : BUFFER integer RANGE 0 TO 9);
END mod_10_count ;
ARCHITECTURE arc OF mod_10_count IS
BEGIN
PROCESS (n_cp, n_rd)
BEGIN
IF (n_rd='0' OR q=9) THEN
q <= 0;
ELSIF (n_cp'EVENT AND n_cp='0') THEN
q <=q+1;
END IF;
END PROCESS;
END arc;
- 20Mhz 를 1초로 분주시오
library ieee;
use ieee.std_logic_1164.all;
entity divone is
port(clk : in std_logic;
clk_one : buffer std_logic);
end divone;
architecture arc of divone is
begin
process (clk)
variable cnt : integer range 0 to 1999999;
begin
if (clk'EVENT and clk='1')then
if (cnt=1999999)then
cnt:=0;
clk_one <= not clk_one;
else
cnt:=cnt+1;
end if;
end if;
end process;
end arc;
- 2상 여자 Stepmotor 구동기를 설계하시오
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY step IS
PORT(clk : IN STD_LOGIC;
clock : buffer std_logic;
q : OUT STD_LOGIC_VECTOR(3 downto 0));
END step;
ARCHITECTURE arc OF step IS
type state_type is (s0, s1, s2, s3);
SIGNAL state: state_type;
BEGIN
process(clk)
variable cnt : integer range 0 to 49999; --49999 적정
begin
if (clk'EVENT and clk='1') then
if (cnt=49999)then
clock <= not clock;
cnt:=0;
else
cnt:=cnt+1;
end if;
end if;
end process;
PROCESS (clock)
BEGIN
IF clock'EVENT AND clock = '1' THEN
CASE state IS
WHEN s0 => state <= s1;
WHEN s1 => state <= s2;
WHEN s2 => state <= s3;
WHEN s3 => state <= s0;
END CASE;
END IF;
END PROCESS;
WITH state SELECT
q <= "1100" WHEN s0,
"0110" WHEN s1,
"0011" WHEN s2,
"1001" WHEN s3;
END arc;
